1. Field of the Invention
The present invention relates to data communications between a data processing system and its associated peripheral devices and, in particular, to an improved universal asynchronous receiver/transmitter (UART) device. According to a first aspect of the invention, multiple data bytes can be transferred from the UART in a single access without checking the error status of each individual byte transferred. According to a second aspect of the invention, the multiple-channel UART allows concurrent writes to the same register of each channel's identical register set. According to a third aspect of the invention, the UART processes any control characters or errors received by the UART during a direct memory access (DMA) transfer while either internal or external first-in-first-out (FIFO) memories are being used.
2. Discussion of the Prior Art
Data communications is a broad term used to define the transmission of data from one point to another.
To ensure coherent data communications between two or more points, e.g. between a data processing system and one of its peripheral devices, an interface standard is established to define the characteristics of the communication link.
The most popular interface standard for data transmission is asynchronous communication. This standard specifies that each data character to be transmitted be proceeded by a "start" bit and be followed by one or more "stop" bits. Between characters, a mark condition is continuously maintained. Because each transmitted character is bracketed by these "start" and "stop" bits, the receiver is resynchronized with each transmission, allowing unequal intervals between characters.
One commonly used asynchronous data communications device is the Universal Asynchronous Receiver/Transmitter, or UART. A conventional UART relies on two separate serial shift registers, each with its own serial port and clock, to receive data from and transmit data to a modem or peripheral device in response to control signals from the associated data processing system. This architecture allows data to be simultaneously sent and received through the UART at different data rates.
To transmit data from its associated data processing system to a selected modem or peripheral device, a UART can request the parallel transfer of data (typically an 8-bit character, or byte, which is placed on the system's data bus) into the UART's transmitter holding register. The transmitter holding register then transfers the data to a transmitter shift register which serially transmits each bit of data to the peripheral device. Initially, when the transmitter holding register is empty, the UART signals the CPU that it is ready to receive data. Data is transferred when a data strobe input from the system to the UART is appropriately pulsed.
Since the transmitter holding register is "empty" as soon as the parallel transfer of data to the transmitter shift register occurs, even if the actual serial shifting of data by the shift register is not complete, the UART can indicate to the data processing system that a new data character may be loaded into the holding register. When the new data is loaded into the holding register, if the serial transmitter shift register is not yet free, then the data is held in the holding register until the serial shift of the initial data is completed. The transfer of the new data into the shift register is then allowed to take place.
Thus, a conventional UART can retain a maximum of two data characters for transmission from its associated data processing system. If the full transmission requires the transfer of more than two characters, then the data processing system, which can transfer data much faster than the UART's transmitter shift register, must either wait for the shift register to complete its serial transfer or undertake different tasks and then respond to multiple interrupts from the UART to complete the transmission. Both alternatives are an extremely inefficient use of data processing time.
Receipt of data by the data processing system from a modem or other peripheral device via the UART is subject to the same time inefficiencies as is data transmission. That is, the processor is inhibited by the operating rate and data capacity of the UART's receiver section. As in data transmission, to receive data, the UART utilizes a shift register and a holding register. A data character is shifted serially from the modem or peripheral device into a serial-to-parallel receiver shift register. When the entire data character has been assembled in the shift register, it is transferred to a receiver holding register, freeing the receiver shift register to receive the next character from the transmission line. The UART indicates to the processor system that it has received data ready to be transferred and places the data on the system bus for parallel transfer when the appropriate strobe is received from the system.
UARTs may be used either in an interrupt mode or in a polling configuration. In the interrupt configuration, the UART sends an interrupt to the data processing system which services it by either placing data on or retrieving data from the system bus. Because a conventional UART can only retain a single data character in each of its receiver and transmitter holding registers, multiple interrupts are required if many data bytes are to be transmitted or received.
To reduce the interrupt overhead of the processor, a more recent UART design has replaced the single-byte receiver and transmitter holding registers with multiple-byte first-in-first-out (FIFO) memories. The National Semiconductor Corporation NS16550A UART utilizes two user-selectable 16-byte FIFO memories as transmitter and receiver buffers. These transmitter and receiver FIFOs permit accumulation of data characters within the UART, eliminating the requirement for multiple interrupts to the processor in its transmission and receipt of data A UART of this type is described in pending U.S. patent application Ser. No. 924,797 filed Oct. 30, 1986 by Michael et al for ASYNCHRONOUS COMMUNICATION ELEMENT, now U.S. Pat. No. 4,823,312; the just-identified Michael et al application is hereby incorporated by reference to provide additional background information for the present invention.
Although the NS16550A UART is a highly advanced device, its status indications are based primarily on single byte error indications.
In the vast majority of cases, data that has been received by the UART is error free. Conventional status indications, however, have not allowed the data processing system to detect the number of consecutive error-free data bytes in the receiver FIFO. This prevents the removal of consecutive data bytes by the data processing system until the status for each byte is first read. Since the status of error-free data is inconsequential, a considerable portion of the access time of the data processing system is being wasted, i.e. two clock access for each data byte to be read in the case of error-free data.
UARTS are also available that provide multiple channels for asynchronous communications between a data processing system and a number of associated peripheral devices. Each UART channel includes its own register set, identical to the register set of each of the other channels. This register set stores information that characterizes the channel relative to its operation. Typically, the register set of each channel is loaded with the appropriate digital information on initialization of the UART; this information may then be modified dynamically to meet changing operating requirements. A problem inherent in conventional multi-channel UARTS is that, although it may be desired to load identical information into corresponding registers of each channel, this information must be sequentially loaded into the registers of individual channels. Thus, the loading of the registers with identical information, both upon initialization and upon dynamic modification wastes valuable processing time.
The transfer of data in a data processing system can be generally referred to as one of three basic types: I/O mapped, memory-mapped or direct memory access (DMA). I/O-mapped and memory-mapped transfers and require processor intervention, thus tying up the processor during the time that data transfers are being implemented. In DMA transfers between a peripheral device and system memory, a path is provided for direct data transfer without processor intervention. Thus, utilizing this path, the peripheral device can transfer data directly to or from the memory at high speed while freeing the processor to perform other tasks during the transfer.
Unfortunately, the DMA capabilities of conventional UARTs do not allow for the handling of control characters, errors or varying amounts of data received by the UART during DMA while using either internal or external FIFOs. Conventional UARTs do not distinguish between control characters, errors or varying amounts of valid data before requesting a DMA transfer. Thus, the data processing system must either resolve all exceptional data cases or prevent DMA transfer of received data. However, as stated above, since most of the received data are valid and without exceptions, the UART need only request processing time for data transfers when it detects an exceptional data byte.